1. Field of the Invention
The present invention relates to a semiconductor device. The present invention particularly relates to a semiconductor device having a memory.
2. Description of the Related Art
For a semiconductor device having a memory, the performance of the memory is very important in determining the performance of the semiconductor device. For example, in a semiconductor device having a CPU and a memory, instructions to be processed by the CPU and data necessary for the processing need to be stored in the memory. Also, the processing by the CPU proceeds by sequential reading of the data from the memory. In other words, in order to perform accurate processing, there should not be even a single defective memory cell. Therefore, in order to improve the yield of a semiconductor device, it is often the case that a spare memory cell is provided in advance (for example, Reference 1: Hisashi Hara, “VLSI Introductory Series 5, Basics of MOS Integrated Circuits”, First Edition, Kindai Kagaku sha Co., Ltd., May 1992, pp. 61-66). A spare memory cell refers to a circuit which is used instead when there is a defective memory cell, which can improve the yield of a semiconductor device.
However, the use of a spare memory cell requires the blowing of three fuses as described in Reference 1. One of the fuses needs to be blown to make a word line connected to a defective bit unusable, and the other two need to be blown to make the potential of a spare word line “high”. As a result, the blowing of fuses takes time, and when a large number of fuses need to be blown, the time required becomes inconvenient. Furthermore, when a plurality of spare memory cells are provided, blowing fuses takes an enormous amount of time.